Associative memory system



Feb. 15, 1966 A. D. FALKOFF 3,235,845

ASSOCIATIVE MEMORY SYSTEM Filed Dec. 28, 1960 10 Sheets-Sheet 1 ORDINAL H B IT AG TAG REGISTER REGISTER 2s TAG 26 BIT TAG REGISTER MATCH OUNTER INDICATOR 262 a 4 2 1 0R T e 22 COUNTER DECODER I6 ASSIGNED ORDINAL REGiSTER FIG. FIG.

INVENTOR ADIN D. FALKOFF FIGJ BY Feb. 15, 1966 A. D. FALKOFF 3,235,845

ASSOCIATIVE MEMORY SYSTEM Filed Dec. 28, 1960 10 Sheets-Sheet 2 COUNTING MULTIPLE i0 CIRCUIT COUNT 52 24 5 72 {8 DETECTOR 20 7 DATA ME MORY PULSE GENERATOR 4 I24 I72 ITS FIG.Ib

Feb. 15, 1966 A. o. FALKOFF ASSOCIATIVE MEMORY SYSTEM 10 Sheets-Sheet 6 Filed Dec. 28, 1960 FIG.40

E I I ssu T L i q b A B F Feb. 15, 1966 A. o. FALKOFF 3,235,345

ASSOCIATIVE MEMORY SYSTEM Filed Dec. 28, 1960 10 Sheets-Sheet 7 Feb. 15, 1966 FALKQFF 3,235,845

ASSOCIATIVE MEMORY SYSTEM Filed Dec. 28, 1960 10 Sheets-Sheet l0 RETURN TO -1 t: FOR MATCH RESPONSE ON LINE 262 AFTER FOR NON-MATCH RESPONSE ON A NON-MATCH RESPONSE-GO TO K-4 LINE 258-RETURN TO '3 FOR NON-MATCH RESPONSE ON FOR MATCH RESPONSE ON LINE 258-60 TO -3 LINE 260-RETURN T0 -2 MULTIPLE COUNT RETURN TO fiI-I AND REPEAT STEPS 15-20 MULI PLE RETURN TO -I ANO REPEAT STEPS I5-2O MULTIPLE COUNT 1 '2I 22 25 24 25 26 27 28 29 United States Patent 3,235,845 ASSOCIATIVE MEMORY SYSTEM Adin D. Falkofl', Croton-ou-Hudson, N.Y., assignor to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed Dec. 28, 1960, Ser. No. 78,999 12 Claims. (Cl. 340-1725) The present invention relates to a memory system and more particularly to a tag memory useable for assigning sequential tag numbers to words randomly arranged in a data memory in accordance with Weighted criteria.

An associative memory system may be described generally as a system which includes a data or word memory in which information words are stored and a tag memory in which identifying tags for the information WOrds are stored. It is sometimes desirable to store words randomly in a data memory and to thereafter assign tags to the words in accordance with weighted criteria such as numeric orders.

In accordance with the principles of the present invention there is provided a novel and improved memory system and more specifically a memory system in which words are randomly stored in a data memory with which there is associated a tag memory for recording tags indicative of some logical order of the randomly stored words. Also associated with the data memory is a bit tag register for keeping track of the bits of words that have been interrogated.

This invention is based upon a search procedure in which items to be sorted are first stored in a data memory, and are thereafter examined binary bit by binary bit in order to assign appropriate sequential tags. As successive binary bits of a group of binary words are examined, starting with the high order or most significant digit, the group of words containing significant digits in the successive orders becomes smaller until a single word is found containing a significant digit in a particular order. That single word will be the numerically largest word in the group.

Examination of each order generally will establish subgroups of words which will subsequently be examined in successively lower orders to establish the sequence of the words.

This invention includes a feed back feature whereby, eacn interrogation of a group of words defines the words which will be included in the group to be examined in the next lower order. Where a binary 1 is sought in the various orders, an output is derived only from those words in which the examined order contains a binary I. These outputs define the words of the next group.

It is a primary object of this invention to provide a system for ordering stored data in accordance with weighted values assigned to stored data.

Another object of this invention is to provide a system for interrogating numerical words in the memory and assigning sequential tags to the words in accordance with their numerical values.

A further object of this invention is to interrogate data stored in a data memory in binary form and to assign ordinals to each data word in accordance with the sequential numerical value of the binary words in the data memory.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.

In the drawings:

FIG. 1 shows the arrangement of FIGS. la and lb.

FIGS. la and 111 form a diagram of the system in block form.

FIG. 2 shows the arrangement of FIGURES 2a, 2b and 2c.

FIGS. 2a, 2b and 2c are a circuit schematic of the system.

FIG. 3 is a bistable storage circuit.

FIG. 4a is a read out circuit for a bistable storage circuit.

FIG. 4b is a diagrammatic illustration of the circuits shown in FIGS. 3 and 4a.

FIG. 5a is a compare circuit used with a bistable storage circuit.

FIG. 5b is a diagrammatic illustration of the circuit shown in FIG. 5a.

FIG. 6 is a schematic representation of data stored in a data memory and the steps followed in assigning ordinals to the stored data.

FIGS. 7a and 7b are timing charts.

General description Referring to FIGS. 1a and 1b, a block diagram is shown of the overall system. The system as illustrated herein is based upon a data memory 10 consisting of 16 eight bit words. All other parameters of this system are designed to be compatible with this 16 word eight bit memory. However, it will be apparent that the data memory may be of any practical size both in words and in bits per word and that necessary changes will be made in other parts of the circuit in accordance with the size of the data memory.

An ordinal tag register unit 12, sometimes referred to as an OT register unit, is provided which has a capacity for storing a number equal to the total of words of the data memory unit 10. The ordinal tag register unit 12 consists of i6 five position binary registers, one associated with each word of the data memory. A bit tag register unit 14, sometimes referred to as a BT register unit, is provided which has a capacity for storing a number equal to the total of bits in the data memory words. The bit tag register unit 14 consists of 16 four position binary registers, one associated with each word of the data memory.

A gate unit 16 having 16 gates, one associated with each Word of the data memory, is provided for simulating responses in instances to be described hereinafter. A counting circuit 18 is adapted to count the number of words of data memory which respond during each interrogation. A multiple-count detector 20 is associated with the counting circuit 18 to indicate one of three conditions as follows: (I) none of the words responded to an interrogation, (2) a single word responded, and (3) more than one word responded.

An ordinal tag register counter 22, sometimes referred to as an OTR counter, is associated with the ordinal tag registers and the counting circuit to count the number of words responding to each interrogation and to enter this count into OT registers corresponding to the responding words.

A bit tag register counter 24, sometimes referred to as a BTR counter, is associated with the bit tag register unit to keep track, for the various words of data memory, of the bit positions interrogated, and to enter this number into appropriate positions of the bit tag registers 14 as required. A decoder 26 is associated with the bit tag register counter 24 and the data memory 10 to condition appropriate bit positions of the data memory for interrogation. A tag match indicator 28 is associated with the ordinal tag register 12 to indicate one of three conditions during interrogation. The first condition indicates that none of the ordinal tag registers responded to an interrogation; the second condition indicates that at least one ordinal tag register responded to an interrogation, and the third condition indicates that, after having received a "no response indication during one interrogation, a response was received on the next interrogation.

The various word positions and corresponding components are designated generally by a number, for example, 10, 12, 14, 16, 18 and 20. The words of data memory 10 are designated 101, 10-2, 103, etc. The bit positions are designated 1 through 8 in accordance with the order of interrogation, starting with the high order. Similarly the word and bit positions of registers 12 and 14; and units 16, 18 and 20 are designated by the general number designation and an appropriate suffix representative of the word number.

As assigned ordinal register 30 is associated with the ordinal tag register counter 22 and is used to store the highest finally assigned ordinal during a tagging operation.

A pulse generator 32 is provided to generate the various pulses and series of pulses required for the operation of the system.

In the operation of the illustrated system, words consisting of binary numbers up to eight binary bits are randomly stored in a data memory. The primary function of this system is to operate upon the binary numbers in such a manner as to assign ordinals to those numbers in accordance with their numerical values. It is possible to assign the lowest ordinal to either the highest number or to the lowest number and to assign the next lowest ordinal to the next number, etc. In the system described herein, the highest number is assigned the lowest ordinal. However, it will be understood that the lowest ordinal could be assigned to the lowest number.

The general operation of the system is as follows:

(1) Enter binary words randomly in the data memory.

(2) Count the number of words in the data memory and enter this tag number (ordinal) in the tag register associated with each word.

(3) Interrogate the high order position of all words in the data memory for the presence of a binary 1.

(4) Count the number of responses (1s) and enter this count in the tag registers for the word positions which respond, replacing the previously stored number (ordinal) in these registers, but leaving the former ordinal in those ordinal tag registers corresponding to words that did not respond in the last interrogation.

(5) interrogate the second highest bit position of those words which last responded and count the number of responses (ls). Enter this count in the tag registers for the words now responding. This last number will again replace the number previously stored in the tag registers corresponding to the words that last responded.

(6) Repeat step 5 with successively lower bit positions until only a single response (1) is counted. Enter the ordinal 1 in the tag register corresponding to the word position which last responded, replacing the ordinal previously stored therein. The word having the ordinal l assigned thereto now corresponds to the largest number (word) in the data memory.

(7) Interrogate the tag registers for ordinals, 2, 3, 4, etc. in ascending order. At some point a hiatus will appear in this sequence, unless the sorting of all numbers is already completed. Enter the highest ordinal found in the sequence before the hiatus in an assigned ordinal register. This ordinal is designated P.

(8) Continue the interrogation for each higher ordinal until the first higher ordinal recorded in the tag register, after the hiatus, is found. This next higher ordinal is designated Q.

(9) Interrogate the appropriate bit positions of the items having the ordinal Q.

(10) Count the number of responses (PS), and add this count to the ordinal P in the assigned ordinal register. Enter this sum in the tag registers corresponding to the words which responded to this last interrogation.

(11) Repeat the interrogation on successively lower bit positions of this last group of words as in step 6, adding the value P from the assigned ordinal register to each count of responses, until a single response is received.

(12) Assign the ordinal P+1 to the single word which last responded.

(13) Repeat step 7 starting the interrogation with the value P+2 and enter the new value P in the assigned ordinal register.

(14) Repeat steps 8, 9, l0 and 11 until the sequence of steps results in a single response.

(15) Repeat steps 13 and 14 until no hiatus is found in the sequence of assigned ordinals. The sorting is then complete and each ordinal tag register contains an ordinal corresponding to the sequential position of the correspond ing word in data memory.

In sorting the numbers from 0 to Nl, where N=2- the number of sequences ending in a single count will be N/2, and the average length of a sequence (number of bit interrogations) will be just two, if the first count of items is included as one interrogation. The total number of interrogations will thus be simply N. This follows in part from the fact that, with binary numbers, every odd number differs from the next lower even number only in the last bit position. Consequently, each time an odd number is identified, an even number is identified also. In such a set of numbers the number of ONE-bits will be NXn/Z, and each ONE-bit will be counted just once.

The time to sort this set of numbers can then be expressed as where t is the time for one count, t, is the time for a bitposition interrogation, and t is the time for carrying out the logical operations at the end of a sequence. Using the values t t l )LSCQ, and t 10 used, which are not unreasonable with present technology, the time to sort 2 items will be about milliseconds. The time for 2 items will be 213 milliseconds. It is noteworthy that the time to sort N items is very nearly linear with respect to N.

For any large set of densely packed numbers (.r, x+l, x+2 x+N-1) the formula holds approximately. The number of sequences remains N/Z, the number of individual bit interrogations will be increased at most by the number of superfluous bits used in expressing a number of the set, and the number of extra counts will be no more than the total number of superfiuous bits.

An upper bound for the more general case of 2" N 2 items of bit-length w, where w is greater than n, can be estimated as follows: Since each sequence identifies at least one number there will certainly be fewer than N sequences. Only one sequence will start with the first bit and one at most will start with the second bit. Two sequences may start with the third bit, four with the fourth, eight with the fifth, and so forth. Thus, the maximum possible length of a sequence decreases as the probability of its occurrence increases, and for large N the average length of a sequence will certainly be less than w/Z. Thus, the number of interrogations will be less than N w/2. Again, the occurrence of ONES and ZEROS will be about equal, and the maximum number of counts will also he N w/2; although in general all the ONES may not be counted.

An estimate of the longest time to sort a set of items under these general conditions is then For 4000 items, 36 bits long, using the values for 1 1,, and t above, the time will be 184 milliseconds.

Apart from the time estimates, this sorting method is inherently efiicient. In contrast to procedures which match word against word and use the same information many times, this method uses each bit only once at most. On the average, the total number of interrogations required to sort N numbers is 1.5N.

If fields of greater length than the data memory Word must be sorted, a partial sorting can be carried out on the first word-length and then continued on the balance of the record, either by holding the entire record in successive Word positions or by emptying the data memory while holding the ordinals, and entering the balance of the record in corresponding memory positions. Similarly, if it is necessary to sort on only a portion of a record while related data is carried along as ballast, the original count of items can be entered only into the tag positions corresponding to the sorting fields.

The algorithm can be used directly for finding the best match" to a given bit pattern. Instead of interrogating on ONES, any arbitrary bit pattern-in any order-could be used as an ordering criterion. A hierarchy of closenessof-match will be established by the ordinals found by the algorithm. To do this it would only be necessary to hold the model bit pattern in the interrogation register and appropriately program the decoder associated with the bit tag register. This kind of use suggests itself very strongly for lexical applications.

Ordinal tag register and ordinal mg register counter The basic circuit of the ordinal tag register 12 and the ordinal tag register counter 22 is shown and described in application Serial Number 809,808, filed April 29, 1959, now Pat. No. 3,093,814 on behalf of Eric G. Wagner and John McCarthy and assigned to the assignee of this invention.

A three digit, three register circuit is described in the above application, but it will be obvious that it can be expanded as desired, for example, to the five digit sixteen register circuit required for the ordinal tag register 16. Similarly, the illustrated three digit input register may be expanded to the five digit ordinal tag register counter 22.

Referring to FIGS. 1, 2a, 2b and 2c, since applica 1 tion Serial No. 809,808 shows a circuit which is the same as the ordinal tag register 12 and the ordinal tag register counter 22 taken together, the units 12 and 22 will be described and it will be understood that they function the same as the circuit in the above application except for certain added features which will be pointed out. The OTR counter 22 corresponds to the input register of the circuit in application Serial Number 809,808 and the OT registers 12-1 through 1246 correspond to the registers A, B and C of the above application.

Each OT register 12-1 through 1246 comprises five bistable storage deviccs 40 only the two left hand ones and the right hand one of rows 1, 2 and 16 being shown in FIG. 2a. The OTR counter 22 comprises five bistable storage devices 42, only the two left hand ones and the right hand one being shown. The binary l outputs from the devices 42 in the OTR counter are coupled through AND gates 52 to complement inputs C of associated devices 40 in the OT registers so that groups of these devices 40 can be complemented under control of the data stored in the OTR counter. With this arrangement, a tag which is entered in the OTR counter can be entered into any or all of the OT registers by first complementing each of the OT registers in accordance with the tag stored in the OTR counter, then resetting the devices 40 in the particular OT register or registers in which the tag is to be stored, and then again complementing all OT registers in accordance with the tag in the OTR counter, as described in the above application.

An operation similar to the operation of entering information into the OT registers may be employed to compare the tag in the OTR counter 22 simultaneously with the tags stored in all the OT registers. This comparison operation is similar to the above described reading opera tion in that the OT registers are complemented and later are recomplemented in accordance with the tags stored in the OTR counter. The simultaneous comparison is achieved by applying a read out signal to the output circuit for all OT registers after the first complement opera tion and prior to the second complement operation. An output is realized only from the particular ones of the OT registers which store the same tag as is stored in the OTR counter.

The OT register unit 12 includes 16 horizontal rows of live [lip-flops 40, each row constituting an OT register. A row of five flip-flops 42 serves as the OTR counter. Each of the ilipfiops 40 and 42 is bistable and, as is usual in binary systems, each flip-flop stores a binary l in one of these states and a binary 0 in the other of these states. Each of the [lip-flops 4t) and 42 is of the well-known type usually termed a complementary flip-flop. This means that the flip-flop may be complemented, that is, switched from the state it is in to its other stable state in response to an input applied at a complement input terminal. The complement input for each of these triggers is designated by the letter c and is located at the center of the lower portion of the block diagram for the flip-flop. The fiipflop may be set to its 0 and 1 states by inputs to the 0 and 1 input terminals respectively. The 0 and 1 inputs are located at the lower left and lower right corners respectively of the fiip-fiop block diagram.

The tag to be entered in the OT registers 12 is first placed in the OTR counter 22. Initially the OTR counter is set to 0 by a pulse on a line 45 and thereafter, successive count input pulses are fed to the complement terminals of the low order flip-flop 421. Alternate inputs to the low order flip-flop 42-1 generate carry pulses to the higher order flip-flops to register the correct count. The counting pulses may be derived from the counting circuit 18 or from the pulse generator 32 and enter the OTR counter via line 44 or 46 and an OR gate 43. A pulse on a line 48 complements all flip-flops 42. Lines 45 and 47 are connected through OR gates 49 and 49a for setting fiip-fiops 42 to their binary zero and binary one states respectively.

To enter the count from the OTR counter into one or more OT registers 12, a complement pulse from the pulse generator 32 is applied to the OTR counter on a line 50. This pulse is directed as an input to AND gates 52-1 through 52 5, so that output pulses appear at the output terminais of all gates 52 n hich are connected to flip-flops 42 that are in their binary 1 states. Therefore, each fiip flop 40 which is connected to an AND gate 52 which in turn is connected to flip-flop 42 in its binary 1 state is complemented, that is. switched from the binary state that it is in to the opposite binary state. It is immaterial whether or not there is any information in an OT register when the read-in operation is initiated since the tag placed in the OTR counter may be selectively entered into any or all of the OT registers regardless of the original state of that register, without disturbing information stored in the other registers.

The second step in the read in operation is to reset to their binary 0 states, those OT registers in which it is desired to enter the count from the OTR counter. To reset an OT register, a reset pulse from the pulse generator 32 is applied to a line 54. In the above cited application this reset pulse is applied directly whereas, in the present invention, it is gated through AND gates 56 by pulses on lines 37 or (it) from a source described hereinafter. The signals on the lines 87, 60 or 54 are gated through OR gates 57. This reset pulse is applied to the 0 input of all flip-flops 40 in the register to be cleared so that each of these fiip-fiops is reset to its binary 0 state. All OT registers may be reset by coincident pulses on lines 54 and and 55.

The third step in the read-in operation is to apply another complement pulse to line 50. This complement pulse again causes all positions of OT registers 12 which are connected to flip-flops 42 in their binary 1 state to be complemented. Thus, flip-flops 40 which were not reset by the pulse on line 54 are returned to their original states and thus store the binary bits which they contained initially. OT registers 12 which were reset to their 0 state by the pulse applied on line 54 are complemented from the state to the 1 state in accordance with the number in the OTR counter 22. Those flip-flops in the reset OT registers which were connected to the flip-flops 42 in their 0 state did not receive either the first or second complement pulses and therefore remain in the zero state in which they were placed by the reset pulse on line 54.

The OT registers 12 may be interrogated, i.e. searched for particular tags, by inserting the desired tag in the OTR counter 22. The first step in the interrogation op eration is to enter the interrogation tag into the OTR counter. All of the OT registers may be simultaneously interrogated for this tag. First a complement pulse is applied to the line 50, as in the read-in operation. All flip-flops in the OT registers which are connected to gates 52 which in turn are connected to flip-flops 42 that are in their binary 1 state will be complemented. Next, a read-out pulse generated in the pulse generator 32 is applied to an interrogation line 63. This read-out pulse passes through all gates 64 of the register or registers 12 containing the interrogated tag, since all these registers are then in the 0 state, some being in the 0 state because they originally stored a 0 and others being in a 0 state because they were complemented in response to the interrogation tag. The output lines 62 from the OT registers 12 serves as inputs to the corresponding bit tag registers 14. The final step in the interrogation operation is to again apply a complement pulse to the line and thus to the inputs of the OT registers which were pulsed by the first complement signals. The flip-flops in the OT registers are again restored to their original states.

It should be apparent that it is only when the tag in a particular one of the OT registers compares exactly with the tag in the OTR counter that all of the flipflops in that OT register will be in their binary 0 state after the first complement operation, to allow a read pulse on line 63 to reach the output line 62 associated with that OT register. In all other cases, all the binary bits of the tag stored in a particular OT register will not compare exactly with the corresponding binary bits of the interrogation tag in the OTR counter. Thus, one or more of the gates 64 associated with the flip-flops in that OT register will be closed when the read-out pulse is applied to line 63 and, therefore, the read out pulse will not reach the corresponding line 62.

Thus, it can be seen that the operation of reading into and interrogating the OT registers each includes 4 steps with the first, second and fourth steps in each operation being the same. First, the tag which is to be either entered into the OT register or used as an interrogation tag is entered into the OTR counter. Second, a complement pulse is applied to the line 50 to complement the flip-flops in each vertical column of the OT register unit 12 for which the binary value in the corresponding of flip-flop 42 in the OTR counter is one. pulse is applied to line 63 to effect a comparison of the tag in the OTR counter simultaneously with the tags in all the OT registers; or a reset pulse is applied to the line 54 to reset to 0 all of the flip-flops in the particular OT register or registers into which the tag stored in the OTR counter is to be entered. Fourth and finally, in the case of an interrogation operation, a complement pulse is applied to line 50 to reset previously complemented flip-flops to their original state and, in the case of the read-in operation, to enter the tag stored in the OTR counter into the OT registers which were cleared during the third step.

Bit tag register and data memory components The basic circuit for the bit tag register 14 and the data memory 10 are shown and described in application Serial Number 744,157, filed June 24, 1958, now Pat. No. 3,134,095, on behalf of Harold F. Heath, Jr., and assigned to the assignee of this invention.

Third, an interrogation &

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8 Referring first to the bit tag register 14 in FIG. 2, the blocks 65 and 66 shown therein and also labelled T and R0 respectively, correspond to the circuit shown in FIGS. 2 and 9 of the last cited application. The same circuits are illustrated herein in FIGS. 3, 4a and 4b.

Binary trigger circuit Referring to FIG. 3, the cryotron trigger circuit shown therein includes 6 cryotrons K1 through K6 which are connected in two parallel current paths between a pair of terminals 67 and 68, the former terminal being connected to a current source 69 and the latter either directly to ground as shown, or through further superconductive circuits to a common or ground terminal. One of the parallel paths includes the gates of cryotrons K1 and K4 and the control coils of cryotrons K3 and K6, and the other path includes the gates of cryotrons K2 and K3 and the control coils of cryotrons K4 and K5. Binary 0 inputs for the circuit are applied through a line 71 to the control coils of cryotron K1. Binary 1 inputs are applied through a line to the control coil of the cryotron K2. When the circuit is in the binary 1 state, the cryotrons K2, K3 and K6 are resistive and, when in the binary 0 state, the other three cryotrons are resistive, as is indicated by the 1 and "0 designations in the blocks representing the gates of these cryotrons. When in either of these states, the current from the source 69 is entirely in the path including the superconductive cryotron gates. Cryotrons K3 and K4 may be termed cross-coupled cryotrons since their coils and gates are connected in different paths so that they are effective to maintain the circuit stably in the binary 0 and binary 1 states, respectively. The state of the circuit is manifested by the condition of the gates of cryotrons KS and K6, the former being resistive and the latter superconductive when the circuit is in the binary 0 state and the condition of each being reversed when the circuit is in the binary 1 state. Lines 72 and 73 represent the control windings of output cryotrons K5 and K6 respectively. The cryotrons K7 and K8 are termed enable cryotrons and have their gates connected across the gates of input cryotrons K1 and K2, respectively. These cryotrons must be driven resistive before inputs applied to the O and 1 input lines 70 and 71, which are connected to the coils of cryotrons K1 and K2, respectively, are effective to change the stable state of the circuit. The enable inputs are applied to a line 74 which is connected to the control coils for cryotrons K7 and K8 and it is only when a. signal is applied to this line that the state of the trigger may be altered by applying an input signal to one or the other of the lines 70 and 71.

Read out circuit FIG. 4a shows two positions of a register wherein binary information is stored in two addressable triggers such as trigger 65. These two positions are connected in one column of an array of columns and rows of memory positions. The circuitry 66 shown associated with these triggers is also designated R0 for read out and is employed to selectively read out the information stored in the triggers 65U (for 65 upper) or 65L (for 65 lower). The read out circuit RO which is associated with the trigger 65U includes a pair of cryotrons K7 and K8, the states of which are controlled in accordance with the value stored in the associated trigger. Similarly, the read out circuit associated with the trigger 65L includes a pair of cryotrons K9 and K10, the states of which are controlled in accordance with the valves stored in the associated trigger 65L. Each of these read out circuits is also provided with a pair of enable cryotrons which, in the read out circuit associated with trigger 65U, are designated K11 and K12, and, in the read out circuit associated with the trigger. 65L, are designated K13 and K14. The state of the cryotrons of K11 and K12 is controlled by enable signals which are applied to an enable line 62U and, similarly, the state of cryotrons K13 and K14 is controlled by enable signals applied to an enable input designated 62L. The output leads for these enable lines are also designated 62U and 62L and each of these leads may be connected to further read out circuits which are to be enabled in response to signals applied to input leads 62U and 62L. The read out current for the circuit is applied at a lead 77 which is steered to one or the other of two output leads 78 and 79 for the particular column in which the triggers 65U and 65L are connected. When the current on lead 77 is steered to terminal 78, it indicates that the particular one of the triggers in that column then being interrogated is in the binary one state, and when current is steered to lead 79, it indicates that the trigger being interrogated is in the binary zero state.

The particular one of the triggers which is interrogated when a read out pulse is applied to lead 77 is controlled by the application of an enable signal to a selected one of the enable lines 62U and 62L. For example. consider the case where trigger 6SU is in the binary zero state and it is desired to interrogate the state of this trigger. In this case, cryotron K7 is resistive and cryotron K8 is superconductive, In order to interrogate this trigger, it is necessary to apply an enable pulse to lead 62U and thereby drive enable ci'yotrons K11 and K12 resistive. No signal is applied to enable lead 62L so enable cryotrons K13 and K14 remain in a superconductive state. When, with the cryotrons in this condition. a read out pulse is applied to lead 77, since cryotrons K7, K11 and K12 are resistive, the current is directed through the then sup;rconductive cryotron K8 to a terminal 80. In the present invention current is constantly applied to the line 77 and the read out is controlled by the enable pulses on line 62. In this mode of operation. the current output wil be maintained between enable pulses on either line 78 or 79. persisting in that parallel branch in which it was forced when the previous enable pulse was applied. The current then passes through the enable cryotron K14, which is then in a superconductive state. to output lead 75 to indicate the binary rero condition of trigger 65U. Similarly, when the trigger 65U is in the binary one condition, the current from line 77 is directed through the then superconductive cryotron gate K7 to a terminal 81 and thence through enable cryotron K13 to terminal line 78, thus indicating the binary one stored in trigger 6SU. The operation is similar when it is desired tointerrogate trigger 65L with the exception that, in this case, an enable pulse applied to lead 62!. to drive enable cryotrons K13 and K14 resistive. and no pulse is applied to enable lead 62U so cryotrons K11 and K12 remain in a superconductive state.

Since, as in the above described interrogation, the enable cryotrons KH and K12. provide a superconductive shunt for cryotrons K7 and K8, the current from line 77 is steered to lead 78 and 7) in accordance with the state of cryotrons K9 and Klfl which are controlled in accordance with the value then stored in trigger 65L. It can be seen that any number of read out circuits for triggers such as 65!.) and 65'l... may be connected in this manner with all of the zcro representing cryotrons in one parallel circuit extending from line 77 to the binary one output lead 78, and all of the one representing cryotrons connectcd in another parallel path from line 77 to the binary zero output lead 79 for the column.

Each of the binary one and zero representing cryotrons are provided with shunting enable cryotrons such as are shown in FIG. 411 so that any particular one of the triggers in the column may be interrogated by energizing the particular enable lead for the read out circuit associated with that trigger.

In the circuits of FIGS. 20, 2b and 2c the circuits 65 and 66 are represented by the block diagram shown in FIG. 4/).

Compare circuit Referring to FIG. in, there is shown a compare circuit 82 which is utilized during interrogation of the state of a trigger such as the trigger 65 described hereinbeforc with reference to FIG. 3. In FIG. 50, only the output coil leads 72 and 73 from the trigger 65, represented in block form, are illustrated. The coils connected to these leads control the state of cryotrons K16 and K17 respectively, which correspond to the output cryotrons KS and K6 shown in FIG. 3. This compare circuit is operable to steer a supply current to one or the other of two output terminals or leads in accordance with whether the interrogation input compares or does not compare with the value stored in an associated trigger 65. This circuit includes the gates of six cryotrons K16-K21. One or the other of the cryotrons K16 and K17 is resistive in accordance with the value stored in the trigger 65. Cryotrons K18 and K are driven resistive when a signal is applied to a lead 83, indicative of an interrogate input representative of binary zero, and cryotrons K19 and K21 are driven resistive when a signal is applied to lead 84, indicative of an interrogate input representative of binary one. Supply current for the circuit is applied to a lead 85. The output for the circuit is realized at one or the other of two output leads designated 86 and 87. When, upon interrogation, the interrogate input on line 83 or 84 compares with the value stored in the trigger 65, the current is steered from line 85 to line 87; and, when the interrogate input does not compare. the current is steered from line 85 to line 86. In all cases. there is at least one completely superconductive path from the line 85 to either one or the other, but not both, of the lines 86 and 87. For example, when the trigger is in the 1 condition and, therefore, cryotron K17 is resistive and K16 superconductive, the current flows from line through cryotron K16 to a terminal 88. From this terminal, the current will be directed through cryotron K118 to output line 87 when the interrogate input is repre entative of a binary one and, therefore, a comparison is indicated, and through the cryotron K19 to line 86 when the interrogate input is a binary zero and. therefore, does not compare with the value stored in the trigger. Similarly, when the trigger 65 is storing a binary zero, the current from line 85 is directed to a terminal 89 and thence through either cryotron K20 or K21 to line 86 or 87 in accordance with whether the interrogate input is a binary one or a binary zero.

During interrogation of a bit position of the data memcry 10, the only thing of interest is whether a binary one bit is stored in the associated trigger 65. Therefore, in the block representation shown in FIG. 5b, and designated 96 which represents the trigger-compare circuit combination shown in FIG. 5a, only the lines 83. 84, 86 and 87 are shown. Since the output line of one compare circuit 96, in FIG. 26 is the input line 85 of the succeeding compare circuit, only the designation 87 is used in FIGS. 21: and 51: for all input and output lines including those for the high order bit positions of the data memory.

For the purpose of illustrating a mode of operation of this invention in which only binary 1's are sought, it is assumed that a constant current is maintained on interrogate input lines 84 of all comparison circuits 90 shown in FIG. 2c. This may be done by setting a group of fliptlops 91 comprising an interrogation register to the binary 1 state. Hence when a binary one is stored in the associated trigger 65 and a pulse is applied to input line 85, a pulse will emerge on line 87. If a binary zero is stored, the pulse will emerge on line 86. It is to be understood, however, that this implies no loss of generality in the applications and uses of this invention since it is within the scope of application Serial Number 744,157. already referred to. to apply currents to either of the lines 83 or 84 of circuits 90, which currents are indicative of an arbitrary pattern of zeros and ones with respect to which the memory may be interrogated. Thus, in the particular operation to be described, the assumption of a constant current on lines 84 of circuits 90 is equivalent to an interrogation pattern consisting of ones in all column positions.

Bit tag register Referring to FIG. 2b the bit tag register unit 14 consists of 16 horizontal rows, each row consisting of four of the basic components, only the two left hand ones and the right hand one of rows 1, 2 and 16 being shown. The basic component is the combination of an addressable trigger 65 associated with a read out unit 66, as illustrated in FIG. 4b.

An enable line 74 threads each row of triggers 65 whereby and 1 binary bits may be stored therein by pulsing the binary 0 lines 71 or the binary 1 lines 70. It will thus be seen that a binary 0 or a binary 1 may be inserted selectively in corresponding bit positions of an individual bit tag register 14 by pulsing respectively the 0 line 71 or the 1 line 70 while at the same time pulsing the enable line 74 for those BT registers 14 in which it is desired to record the binary bit. It will be noted that pulses on these enable lines 74 are derived from pulses on lines 87 or 60 which are gated through AND gates 56 in the OT register unit 12 by reset-write pulses on line 54.

It has been described hereinbefore how a signal is derived on a particular line 62 when the interrogation of the corresponding OT register 12 shows a comparison with the tag in the OTR counter 22. This signal on the line 62 is effective to read out the binary bits of information in the corresponding BT register 14 and, after having passed through all read out units 66 of that particular BT register, to turn on a corresponding flip-flop 100 which indicates that the corresponding OT register 12 has just responded positively to an interrogation. A response is indicated by a signal on a binary one line 101 whereas a lack of response is indicated by a signal on a binary zero line 102.

A reset line 103 is common connected to the binary 0 terminals of the flip-flops 100 to reset them to O for purposes described hereinafter.

Bit tag register counter In accordance with the mode of operation of this invention, the BT registers 14 which are interrogated at any one time will all contain the same bit position number. The value read out of each bit position of the BT register will be manifested by signals on binary 0 lines 79 or binary 1 lines 78 as described hereinbefore. These signals are fed to the BTR counter 24, FIG. 2b. Inputs to the BT registers 14 are received from the BTR counter on the binary zero and binary 1 lines 71 and 70 respectively, as described hereinbefore.

The BTR counter 24 is similar to the OTR counter 22 and consists of four flip-flops 104 connected in series by lines 106 whereby successive input pulses to the complement terminal of the low order flip-flop 104, through appropriate carries, enters a count of the input pulses into the BTR counter. Only the two left hand flip-flops 104 and the right hand one are shown in FIG. 2b. The binary value in the BTR counter 24 is transferred into BT registers 14 when enable signals are received on the lines 74, as described hereinbefore. The output lines 79 and 78 from the BT registers 14 are fed to the 0 and 1 input terminals respectively of output flip-flops 108. These input terminals are located at the upper sides of the diagrammatic illustrations in FIG. 2b. The output flip-flops 108 are shown as are included in the BTR counter 24. A line 107 is connected through individual OR gates 109 to the binary zero inputs of the flip-flops 104 for resetting them to zero.

The binary values entered in the flipfiops 108 are fed through lines 110 and 112 to the decoder unit 26. The binary states of the flip-flops 108 are also fed through lines 114 and 116 and AND gates 118 and 120 to the corresponding flip-flops 104 which constitute the BTR counter. The binary values in the flip-flops 108 are gated into the flip-flops 104 by a gating signal on a line 122. Counting pulses for advancing the BTR counter 24 are generated in the pulse generator 32 and are fed to the BTR counter through line 124 or line 126.

Data memory The data memory 10 consists of 16 registers each capable of storing a word consisting of eight binary bits. Each bit of this word is stored in an addressable trigger of the type described with reference to FIG. 3. Each addressable trigger has associated therewith a compare unit 82 which is illustrated in FIGURE 5a. Since the manner of entering and storing a word in memory is not a part of the present invention, the storage unit per se, that is, the addressable trigger 65, is not shown but rather the diagrammatic representation of the trigger-compare unit 90, shown in FIG. 5b, is shown in FIG. 2c as representing each bit position in data memory. Only the two left hand columns and the right hand column of units are shown for words 1, 2 and 16. As previously described with reference to FIG. 519, an input to the compare unit 90 will emerge on line 87 if the associated bit position stores a binary digit which matches the interrogation pattern set up in the associated flip-flop 91, and will emerge on the line 86 if the corresponding bit position does not store a matching digit.

The output of each of the BT registers 14 consists of lines 101 and 102, a signal on the line 101 indicating that the corresponding OT register has responded positively to an interrogation and a signal on the line 102 indicating that the corresponding OT register did not respond positively. The signal on the line 102 flows directly through the AND gate unit 16, through the data memory 10, through the counting circuit 18, and through the multiple count detector 20 to ground. Within the gate unit 16 each line 101 feeds to one terminal of an AND gate and also continues on a line 132 to an AND gate 134 associated with a corresponding word in data memory 10. An input line 136 to the gate unit 16 is commonly connected as the second input to all AND gates 130. The outputs of the AND gates 130 are the lines 60 which are the alternate gating inputs to the AND circuits 56 in the OT registers 12.

The previously described line 1.24 which is connected as an input to the BTR counter 24 also serves as an input line to the data memory 10 and is commonly con nected as the gating input to all AND gates 134. A pair of lines 140 and 142 is associated with each column of binary bit registers in the data memory 10, for use in conjunction with the decoder 26 for interrogating one binary bit position of data memory at a time. Each line 140 forms the control winding for a cryotron gate 144 associated with the match output line 87 of each compare unit 90 whereas each line 142 forms the control winding for a cryotron gate 146 associated with the nomatch output line 86 of each compare unit 90 in the associated column. The no-match output line 86 extends through the gate 146 to the line 102. The nomatch line branches through a line 148 and the gate element 144 to the binary 1 line 87. With a current applied to the line 140, the cryotron gates 144 are rendered resistive and current on a no-match line 86 flows to the line 102 and then to ground. When current is applied to the line 142, current fiows through the control winding of cryotron gates 146, rendering the gates 146 resistive and diverting current from a no-match line 86 to the match line 87, thus making a mismatch appear to the next lower binary bit register 90 as a match rather than as a mismatch. The purpose of this circuit is described hereinafter. The pair of lines 140 and 142 associated with the low order bit position registers 90 branch through lines 150 and 152 to the multiple count detector circuit 20 for a purpose described hereinafter.

Referring to FIG, 1, the lines 140 and 142, shown in cable form, pass through a cryotron unit 154. Referring to FIG. 2c, each line 140 includes a cryotron gate element 156. Each pair of lines 140 and 142 is connected by a line 153 which includes a cryotron gate element 169. A line 162 forms the control winding for all cryotron gate elements 156 whereas a line 164 forms the control winding for all cryotron gate elements 160. The lines 162 and 164 are common connected to ground at one end and are selectively connectable to a power source 166 by a switch 168. In the OFF position, the switch 163 is connected to the line 164 Whereas, in the ON position the switch is connected to the line 162. When the switch 168 is in the ON position all outputs from the decoder 26 are on lines 142, since cryotron gates 156 in all lines 148 are then resistive and all cryotron gates 166 are superconductive. Thus, all cryotron gates 146 in the data memory are made resistive and all outputs from compare circuits 90 appears as match outputs regardless of the actual binary state of the corresponding storage trigger. This circuit is necessary to obtain the initial count of the number of words in the data memory 19 to be sorted or ordered. When the switch 168 is in the OFF position, the cryotrons 160 are resistive and outputs from the decoder 26 follow their normal paths in lines 140 and 142. Since the BTR counter has a capacity larger than required to count the binary bits of a data word, a particular count could be used to apply current to all lines 142 and thus eliminate the need for the mask control unit 154.

Decoder The decoder unit 26 may be any conventional type decoder, for example, a relay type the only requirement being that it be capable of energizing particular combinations of lines in accordance with various inputs. In the particular embodiment described in detail herein, the decoder energizes lines 140 and 142 in eight combinations in accordance with the setting of the BTR registers which store the bit position numbers of words in data memory. Eight-bit Words are used and the BTR counter is shown as a four position binary counter. The inputs to this BTR counter are the values between 1 and 8 in binary form. In response to each of these eight possible inputs, the decoder must energize the line 1411 of one pair of lines 141L142 and must energize the line 142 in all other pairs. in counting the bit positions, the number 1 is assigned to the high order bit position of a word of data memory to signify that this is the first bit position interrogated. The next lower order is given the value 2 and so on. The following chart indicates which of the lines 149 and 142 carry current for the eight possible inputs which are represented in binary form.

1N1 l t I llit. lositinn Iiiucslllluud 11L! 1 2 3 l 4 5 l [J 7 1 S wAgiAVl4 1) ll 11 1 I10 14! 142 142 142 .1 142 142 11! ll ll 1 1) M2 M0 1-1. 11! l-l. 14; 142 14; ll (1 1 l 142 I42 [410 .3 l 141: 14! 142 l t! I] 1 (I ll 14*. 142 142 l/Jl 14; 141] 1413 142 i) l U 1 14; 142 1412 142 Mr) 141! 142 142 a 1 1 :1 it: 142 1r: it: 142 1,40 142 142 ll 1 1 1. 14! 142 v 14) 14;! 142 142 140 t 141! 1 U U U 112 142 I 142 i 142 11 143 1 12 1110 While a particular operation has been described, it will be apparent that a programable decoder could be used to select various fields of a data word for interrogation or to select bit positions for interrogation in sequences other than highest to lowest or lowest to highest. The most significant bit should be interrogated first but, since weights other than numeric may be applied to various bits, the most significant bit need not be the highest order bit.

lit

14 Counting circuit Referring to FIG. 1, the counting circuit 18 consists of 16 counting units, each unit corresponding to a word in the data memory 10. The common inputs to the counting circuit 18 consist of 4 lines 170, 172, 174 and 176. These lines receive signals from the pulse generator 32. Individual inputs to the 16 units of the counting circuit consist of the lines 87 and 102 from the corresponding words in the data memory 10. The output from the counting circuit 18 is the line 44 referred to in the description of the OTR counter 22.

Referring to FIG. only the upper two units corresponding to words 1 and 2 and the lower unit corresponding to word 16 are shown. It is seen that each unit of the counting circuit 18 includes a closed loop 179, having an input line 180. It will be noted that the input line 180 of each loop after the first is also the output line of the preceding loop. The left side of the loop consists of a line 132 and a cryotron gate element 184, whereas the right side of the loop consists of a line 186, a cryotron gate element 188 and a delay device 190. The delay device may he a length of transmission line, for example. The line 186 also forms the control winding for a cryotron gate element 192 which is in the line 176. The cryotron gate elements 192, one for each of the 16 counting units of the counting circuit 18 are connected in series. The line 176 also forms the control winding for a cryotron gate element 194 and then continues to ground. The input line 174 includes the cryotron gate element 19-1 and thereafter emerges from the counting circuit 18 as the line 44 which is the input to the OTR counter 22.

The output line 189 of the lower loop 179 is connected to the binary 1 input of a flip-p 198. The input line 179 is connected to the binary 0 input of the flip-flop 198. The binary output of the flip-flop 198 is connected to the output line 177 which in turn is connected to the pulse generator 32.

To illustrate operation of the counting circuit 18. assome, for a particular bit position of the data memory being interrogated, that the odd numbered word positions store a binary l and even numbered word positions store a binary 0. Currents generated in the pulse generator 32 are applied to the lines 170, 176, 174 and 172 in that order.

First, current is applied to the line to reset the lipilop 198 to its binary 0 state. Next, current is applied to line 176 and flows through cryotron gate elements 192 and the control winding of cryotron gate element 194 to ground. rendering the gate 194 resistive. Current is next applied to the line 174 but is blocked by the resistive state or the cryotron gate element 194.

Since the odd numbered word positions of the data memory store binary 1's, the corresponding gate elements 184 will be resistive and current will flow in the right hand lines 186 of the odd numbered loops 179. The gate elements 188 of the even numbered counter units are resistive and current will How in the left hand lines 182 of the even numbered loops. It will be apparent that the currents flowing in the left hand lines 182 merely flow inelfcctively to the next loop 179 where they may be effective to count a binary 1. With the flip-flop 198 reset to 0 and currents applied to lines 176 and 174, current is then applied to the line 172 and, in the first word position. flows through the line 186, through the superconducting cryotron gate element 188 and through the control winding of the cryotron gate element 192 thus rendering gate element 192 resistive and blocking the flow of current in the line 176. Blocking the flow of current in the line 176 permits the cryotron gate element 194 to return to its superconductive state and permits current to flow from the line 174 through the gate element 194. The output on the line 44 is fed to the OTR counter 22 where a count is entered into the counter for each current pulse passed by the gate 194. The pulse applied to the line 172 is delayed in the delay unit and, after this delay. is fed into the next loop 179. In the recited example, the cryotron gate element 188 of this second loop 179 is resistive and the gate element 184 is superconductive, whereby the current fiows through the left hand line 182 to the third loop 179 without delay. This third loop has been defined as having the gate element 184 resistive and the gate element 188 superconductive whereby the current flows again in the right hand line 186 and renders the corresponding gate element 192 resistive, again blocking the current on the line 176 and permitting current to flow in the line 174 to again enter a counting pulse into the line 44. The current on the line 172 flows through the remaining loops 179, being delayed by a delay unit 190 each time a pulse is counted and then proceeding on until it reaches the binary 1 input of the flip-flop 198. When the pulse reaches the flip-flop 198 and switches it to its binary 1 state, the output on the line 177 feeds into the pulse generator 32 and shuts off the pulses to the lines 172, 174 and 176 in that order.

Multiple count detector The function of the multiple count detector 20 is to indicate the number of interrogated word bit positions which responded to an interrogation of a particular binary bit position of data memory for the presence of matches. The multiple count detector consists of sixteen individual units, each corresponding to a word in data memory. The inputs to the individual units are the lines 87 and 102. Two inputs to the multiple count detector 20 are the previously referred to lines 150 and 152 connected to the lines 140 and 142 respectively and leading to the low order bit positions of the data memory words. Another input is a line 200 which receives input signals from the pulse generator 32. The outputs from the multiple count detector are three lines 202, 204 and 206. Current on the line 202 indicates that none of the interrogated word positions responded to an interrogation for a matching bit; current on the line 204 indicates that a single word position responded; and a signal on the lines 206 indicates that more than one word position responded.

The multiple count detector is essentially a cryogenic tree network consisting of 16 units, one unit corresponding to each word of data memory. A first line 208 is connected to a power source 210 and in series through sixteen cryogenic gate elements 212, one associated with each word of data memory, to an AND gate 214. Only the upper two units corresponding to words 1 and 2 and the lower unit corresponding to word 16 are shown in FIG. 20. The output line 87 of each word of data memory forms the control winding for the associated gate element 212.

Between the source of supply 210 and the first gate element 212, the line 208 branches into a line 216 which extends through all sixteen units of the multiple count detector to a second AND gate 218. This line 216 includes l6 cryogenic gate elements 220, one being paired. with each gate element 212. The gate element 220 associated with the first word of data memory is linked by the corresponding data memory output line 102 as a control winding. The remaining fifteen gates 220 are linked by the lines 87 from the corresponding words of data memory.

In each of the multiple count detector units, after the one corresponding to word 1 of data memory, the line 208 branches into lines 222. Each line 222 is connected to the line 208 ahead of the corresponding gate element 212 and, after passing through a cryogenic gate element 224, is connected into the line 216. In each of the multiple count detector units, after the one corresponding to word 1 of data memory, the line 216 branches into a line 226. Each line 226 is connected to the line 216 ahead of the corresponding cryogenic gate element 220 and, after passing through a cryogenic gate element 228, is connected to aline 230 which extends through all units of the multiple count detector, except those corresponding to words 1 and 2 of data memory, and is connected to an AND gate 232.

The input line 200 is common connected as the gating input for the AND gates 214, 218 and 232. If, during an interrogation for binary ls, none of the word positions of data memory respond, current from the source 210 flows through the line 208 to the AND gate 214. Thereafter a signal applied to the line 200 gates the signal into the pulse generator 32 via the line 202 where it is effective to initiate a particular sequence of pulses as described hereinafter If the line 87 corresponding to any word of memory carries a current indicating the presence of a binary 1 bit, the corresponding cryotron gate element 212 is rendered resistive and current on the line 208 is diverted to the line 216 to the AND gate 218 where it is gated by a pulse on the line 200 into the pulse generator 32, via the line 204. Current on the line 216 indicates that a single word of data memory responded with a binary 1 indication and a particular sequence of pulses is initiated as described hereinafter.

After a binary 1 response from any word position, a subsequent binary 1 response from any other word position diverts the current from the line 216 to the line 230 whereby the AND gate 232 is conditioned and a pulse will be fed via the line 206 into the pulse generator Where it is etfective to initiate a particular sequence of pulses as described hereinafter.

Since two or more identical words may be stored in the data memory and since the only way a particular interrogation sequence may be terminated is to obtain a count of only one from the multiple count detector 20, circuitry is provided to give an only one response whenever low order bit positions of a particular group of data memory words are interrogated. This is in no way prejudice to the results since, if more than one word responds to this interrogation they are identical Words.

Lines 208 and 230 include cryotron gate elements 234 and. 236 respectively. A line 238 connecting lines 208 and 216 includes a cryotron gate element 240. A line 242 connecting lines 216 and 230 includes a cryotron gate element 244. The input line 150 forms a control winding for gate elements 234 and 236 and is connected to ground. The line 152 forms a control winding for gate elements 240 and 244 and is connected to ground. When the low order bit position of data memory is interrogated, current appears on the corresponding line 140 and thus on the line 150, whereby gate elements 234 and 236 are rendered resistive. At this time, there is no current on the line 152 and the gate elements 240 and 244 are superconductive. Therefore, current appearing on either line 208 or 230 is diverted to the line 216, thus simulating an only one response. During interrogation of all bit positions of data memory other than the low order bit position, current appears on the line 152 and thus inhibits the connecting lines 238 and 242.

Tag match indicator The tag match indicator 28, FIG. 2b, is associated with the OT registers 12 to indicate one of the three conditions during a particular interrogation sequence. The first condition indicates that none of the OT registers responded positively to interrogation for a matching tag; the second condition indicates that at least one OT register responded; and the third condition indicates that, after having received a non-response indication during one interrogation, a response was received on the next interrogation.

Referring to FIGS. 1 and 2b, the tag match indicator has four inputs 250, 252, 254 and 256. The input 250 is from the OT register unit 12, whereas the inputs 252, 254 and 256 are connected to the pulse generator 32 and received pulses therefrom. The tag match indicator has three output lines 258, 260 and 262 which feed into the pulse generator 32 to initiate particular sequences of pulses.

Referring to FIG. 211, an OR gate 264 in the OT register unit 12 receives the output of each OT register which responds to an interrogation showing that the responding register contains the same tag as that stored in the OTR counter 22. The output of OR gate 264 is fed through the line 250 to the tag match indicator 28 where it is fed in parallel to an inverter 266 and an AND gate 268. The output of the inverter 266 is fed to an AND gate 270. The second input of the AND gate 270 is the input line 252. The output of AND gate 270 is connected to the binary 1 input of a fiip flop 272 and the binary 1 output of the flip-flop 272 is fed in parallel to AND gates 268 and 273. The output of AND gate 268 is connected to the binary 1 input of a flip-flop 276 and the binary 1 output of the flip-flop 276 is fed to an AND gate 278. The binary output of the flip-flop 276 is fed to the AND gate 273. The output of AND gate 273 is fed to an AND gate 274. The input 254 is connected in parallel to the binary 0 inputs of the flip-flops 272 and 276. The binary 0 output of the flip-flop 272 is connected to an AND gate 280. The input 256 is commonly connected to the AND gates 274, 278 and 280. The output of AND gate 274 is the output line 258; the output of AND gate 280 is the output line 260; and the output of AND gate 278 is the output line 262.

The tag match indicator is first reset by pulsing line 254. This resets flip-flops 272 and 276 to their binary zero states. The binary 0 output of the fiip-fiop 272 is gated by a signal on line 256 through the AND gate 280 to the line 260. This is the equivalent of a positive response to the interrogation for an OT register tag matching the OTR counter tag and initiates a particular sequence of pulses in the pulse generator 32.

If the interrogated tag is not present in any of the OT registers there is no output from the OR gate 264 to the line 250. This negative response, when inverted by the inverter 266, appears to the AND gate 270 as a positive response and is gated through by a signal on the line 252 to switch the flip-flop 272 to its binary 1 state. The binary 1 output is fed to the AND gate 273 where it is gated to the AND gate 274 by the binary 0 output of flip-flop 276. The input to AND gate 274 is gated to the line 258 by a gating pulse on the line 256 whereby a particular sequence of pulses is initiated in the pulse generator 32. The binary 1 output of the flip-flop 272 is also fed to the AND gate 268 to condition it for a subsequent positive response on the line 250. When a subsequent interrogation does produce a positive response on the line 250, it is gated through the AND gate 268 to switch the flip-flop 276 to its binary 1 state, closing gate 273. The binary 1 output of the flip-flop 276 is gated through the AND gate 278 by a pulse on the line 256. The signal on the line 262 is fed to the pulse generator 32 where it initiates a particular sequence of pulses.

Assigned ordinal tag register The assigned ordinal register (AO register) is a series of binary flip-flops 289, one corresponding to each bit position of the OTR counter 22. In accordance with the FIG. 2a illustration of the OTR counter 22, only the two left hand fiip-flops 289 and the right hand one are shown. The A0 register 30 is adapted to receive the contents of the OTR counter in response to a gating signal on a line 290. The A0 register also is adapted to enter the contents of the A0 register into the OTR counter in response to a signal on a line 292.

AND gates 294 are connected to the binary 0 output of each flip-flop 42 in the OTR counter. AND gates 296 are connected to the binary 1 output of each of the flip-flops 42. The line 290 is connected in parallel to all AND gates 294 and 296 to gate the contents of the OTR counter to the AO register 30 through binary 0 lines 298 and binary 1 lines 300.

AND gates 302 and 304 are connected to the binary O and binary 1 outputs respectively of the flip-flops 289.

The line 292 is commonly connected to the AND gates 302 and 304 to gate the contents of flip-flops 289 into the flip-flops 42 of the OT R counter through the OR gates 49 and 49a.

Pulse generator The pulse generator 32 may be any suitable generator capable of generating the desired pulses in the desired order. Since the design of a pulse generator is not a part of the present invention and the construction of a suitable one is within the scope of those skilled in the art, the details of a pulse generator are not shown. Instead, a timing chart, FIG. 7, indicates the sequence of the various pulses which are required.

Circuit operation Having described the individual components of the system and the manner in which each functions individually, the system operation and the cooperation of these components in the system will be described. As previously indicated, the function of this system is to operate upon data stored in the data memory 10 in such a man ner as to enter numerical tags or ordinals in the OT registers corresponding to the words in data memory in accordance with the weighted values of information bits comprising the words. The specific operation described is the ordering of binary numbers in accordance with their relative values. It is possible to assign these tags whereby the lowest numbered tag corresponds to either the lowest valued number in data memory or to the highest valued number. In the example described hereinafter, the lowest numbered tag is assigned to the highest valued Word in data memory.

FIG. 7 is a timing chart which is referred to in the description of the system and indicates the sequence of the various signals within the system. Along the top edge of the timing chart are 53 numbered columns which correspond to 53 time periods during operation of the system. Some of the steps which are shown as starting or occurring sequentially. could start or occur coincidentally, but, for simplicity of illustration, are shown as starting or occurring sequentially. Arranged along the left edge of the timing chart are a number of titles which refer to the particular operation which is performed. In an adjacent column numbers are shown which indicate the lines upon which the various signals appear to perform the particular operation.

Also noted at the top of the timing chart are a number of designations alpha 1, alpha 2, alpha 3, alpha 4 and beta 1. These designations and the corresponding vertical lines separate the timing chart into groups of steps, some of which may be repeated during the operation of the system, depending upon the particular responses detected at various times.

Referring to FIG. 6, a schematic representation of the data memory 10 shows 16 words arranged in horizontal rows as in the circuit schematic. The columns numbered 18 correspond respectively to the eight bit positions, with the high order bit position being numbered l, since it is the first bit position interrogated. On the left side of the figure, the words are numbered 1-16 and, as illustrated here are arranged sequentially in accordance with their values 207, 199, 197, 192, 170, 159, 153, 142, 136, 129, l29, 102, 85, 68, 58 and 31 which are indicated in the word value column. However, it will be apparent from the following description that the words may be stored in random order and will be correctly operated upon irrespective of the random arrangement. However, the illustrated sequential arrangement is convenient for purposes of explanation.

In the first column on the left, the ordinals I through 16 are shown. However, it is noted that the 16 words will be numbered 16 through 31, as illustrated in the sec 0nd column from the left, rather than 1 through 16. The purpose of this is to illustrate a versatile feature of the machine in which the capacity of the OTR counter 22 need not be the same as the capacity of data memory or the same as the number of words to be sequentially ordered. It will be apparent from the description that it would be even simpler to arrange a system where the capacity of the OTR counter corresponded exactly with the number of words to be ordered in which case the ordinal 1 could be assigned to the largest word and 16 to the smallest word. While the actual word count in the example is 16, the capacity of the OTR counter is 31 and therefore the difference between the number of words and the full capacity of the counter is added in each case to form the assigned ordinal.

Referring to FIG. 6, the initial word count, supplemented by the difference in the counter capacity is initially stored in each of the OT registers 12 and, as indicated by the fact that the number following the ordinal 31 in the word count column is a 1, this was done on the 0 bit cycle. In other words, it was not done during the interrogation of any one of the eight bit positions. During interrogation of the first bit of all sixteen words, as indicated by the number 1 in the Group I, Interrogation 1 column of FIG. 6, eleven words responded to the interrogation for a binary 1 in this bit position. The bit number 2 is stored in the sixteen corresponding BT register 14, this being the appropriate bit number for the next interrogation of this group of words. The difference in the number of words and the capacity of the counter is 15 and therefore the number 15 is added to the number of responding words, eleven, and the sum 26 is stored in the OT registers 12 corresponding to the eleven responding words.

During interrogation of the second bit positions of this group of eleven words which are designated Group I, only four words responded and therefore the ordinal l9 (15+4) is stored in the OT registers corresponding to these four words, replacing the ordinal 26. The next bit position number 3 is stored in the corresponding BT registers, replacing the number 2. The third bit positions of these last responding four words are interrogated and since all four contain binary 0s in the third bit positions, they do not respond, but a response is simulated, whereby the ordinal 19 is restored again in the corresponding OT registers and the new bit position number 4 is stored in the corresponding BT registers. The fourth bit positions of these four words are interrogated and since all four bit positions contain binary 0s, a response again is simulated and the ordinal 19 is again restored in the corresponding OT registers. The corresponding BT registers are advanced to store the digit 5 representing the next bit to be interrogated. During the fifth interrogation cycle, the fifth bit positions of these four words are examined and only one response is obtained. The OT registers corresponding to the three non-responding words remain set at 19. However, the ordinal 16 (l5-ll) is entered in the OT register corresponding to the responding word and the number 6 is stored in the corresponding BT register.

At this time the first ordinal 16 has been permanently assigned. Also at this time the ordinal 19 is correctly assigned to one of the three numbers in whose OT register it is stored. Similarly the number 26 is correctely assigned to one of the seven words in the corresponding OT registers of which the ordinal is stored, and the ordinal 31 is correctly assigned to one of the 5 words in the corresponding OT registers of which the ordinal 31 is now stored. The processing of a group is completed each time an ordinal is assigned to a single word. Thus, the first group interrogation is ended and the second group interrogation may be started.

Group II includes the remaining three words of the group of words which were initially assigned the ordinal 19. The fifth bit position of the remaining three words having the ordinal 19 need not be interrogated because their failure to respond indicated that their fifth bit positions contained binary 0's and their bit count was advanced to 6 when they were identified by their ordinal 19. Therefore the sixth bit positions are interrogated and only two words respond as having binary 1s. The ordinal l8 (l6-l-2) is stored in the two corresponding OT registers and the ordinal 19 remains in the OT register corresponding to the third word. During the interrogation of the seventh bits of these two words, a single word responds and therefore this word is assigned the next ordinal after the highest permanently assigned ordinal, in this case, the ordinal 17. Since only two words had been assigned the ordinal l8 and one of these ordinals has been changed to 17, the ordinal 18 was properly assigned to the other word. Similarly, since the two of the three words which were assigned the ordinal 19 have been assigned the ordinals 17 and 18, the third word is properly assigned the ordinal 19. This is the end of the second group interrogation.

Group III consists of the remaining seven words which have been assigned the ordinal 26. The second bit positions of these seven words are not to be examined, since it is known by their elimination on the second step of the Group I interrogation that all contain binary 0 in this bit position, and the bit count is advanced to 3. The third bit positions of these seven words are examined and a single word responds. Therefore, the next higher ordinal 20 is assigned to this word and is stored in the OT register corresponding thereto. The number 4 is stored in the corresponding BT register. This is the end of the Group III interrogation which consisted of only one in.- terrogation.

Group IV interrogation is made on the remaining six words which have the ordinal 26. The fourth bit positions of these six words are interrogated and only two words respond. Therefore, these two words are assigned the ordinal 22 (20+2) in the corresponding OT registers and the bit position number 5 is stored in the corresponding BT registers. Interrogation of the fifth bit positions of these two words shows that both contain binary Us and therefore binary 1 responses are simulated to restore the ordinal 22 in the corresponding OT registers. The bit number 6 is stored in the corresponding BT registers. Interrogation of the sixth bit position of these two words results in a response from only one of the two words. This word is assigned the next higher ordinal 21 and, since only two words have been assigned the ordinal 22, the second word has properly been designated 22.

The Group V interrogation is performed upon the remaining 4 words which were assigned the ordinal 26. The interrogation starts in the fifth bit position and results in a response from only two words which are assigned the ordinal 24 (22+2). Interrogation of the sixth bit position of these two words results in a single response and the ordinal 23 is assigned to the responding word. The ordinal 24 remains assigned to the other word.

The Group VI interrogation is performed upon the remaining two words which have the ordinal 26. The interrogation of the fifth and sixth bit positions shows binary 0s in both words. Interrogation of the seventh last bit positions again results in two responses. The ordinal 26 remains assigned to both words. Ordinal 25 will be skipped.

The remaining five words which were assigned the ordinal 31 form Group VII and are interrogated in the second bit positions. Only three words respond. Therefore, these three words are assigned the ordinal 29 (26+3) and the hit number 3 is stored in a corresponding BT register. Interrogation of the third bit positions of the three words results in a single response and the ordinal. 27 is assigned to the responding word.

In the Group VIII interrogation, the two remaining words having the ordinal 29 are interrogated in the fourth bit positions. A single response is received whereby the ordinal 28 is assigned to the responding word and, the ordinal 29 remains assigned to the other word. 

12. A ASSOCIATIVE MEMORY SYSTEM FOR ASSIGNING SEQUENTIAL ORDINALS TO DATA WORDS IN MEMORY IN ACCORDANCE WITH THEIR RELATIVE VALUES COMPRISING, IN COMBINATION, A MEMORY STORING A PLURALITY OF MULTI-ORDER WORDS, EACH SAID ORDER CONSISTING OF AT LEAST ONE INFORMATION BIT, AN ORDINAL TAG REGISTER CORRESPONDING TO EACH SAID WORD, MEANS FOR CONDITIONING SAID MEMORY FOR PARALLEL-BYWORD, SERIAL-BY-ORDER INTERROGATION OF SAID WORDS FOR PARTICULAR DATA, MEANS FOR INTERROGATING SAID MEMORY IN ACCORDANCE WITH SAID CONDITIONING INCLUDING A FEED BACK RESPONSE FROM EACH WORD HAVING SAID DATA IN THE LAST PREVIOUSLY INTERROGATED ORDER FOR INTERROGATING A NEXT ORDER OF RESPONDING SAID WORDS. 